The present invention relates to chip design and manufacturing. More specifically, the invention relates to a chip which includes structures for identifying defects within the chip while at the same time providing a chip which can be properly planarized using a chemical mechanical polishing process (CMP).
Chip design can be very time consuming and thus expensive. Design packages such as, Rapid Chip®, owned by LSI Logic, Corp. simplify the design layout by routing power and ground in a standard pattern which is easier to simulate. Unlike previous designs where power and ground were mostly routed around the periphery of the chip, the standard pattern make power and ground more readily available across the chip.
Another way in which design packages, such as, for example, Rapid Chip® improve the efficiency of chip design is through the use of IP (Intellectual Property) cores. IP cores act as building blocks for chip design by providing pre-designed structure for commonly used components. Rather than designing each component, designers can place these IP cores within their design to improve the efficiency of the design process.
Rapid Chip® packages commonly used IP cores together and therefore provides a base from which the designer can begin to create a custom design. For example, a designer selects a pre-designed chip which includes a number of IP cores which the designer desires to include in his/her chip design. A floor plan is provided by the various HP cores and the designer adds to these IP cores to complete the design. In addition, to the HP cores which the designer desires to include in the chip, the layout will likely include extra IP cores which are not needed in the design and therefore will be inactive. An example of a Rapid Chip® floor plan 10 is shown in FIG. 1. The floor plan includes, for example, a DDR-80 bits core 20, HyperPHY20 channels cores 22, 256×80 Dual Port RAMs core 24, 2M Usable Gates core 26, 2k×80 Single Port RAMs core 28, PLLs cores 30, 10 G Ethernet MAC Logic core 32, and GigaBlaze 8 channels core 34. When designing the metal interconnect portion of the design, the designer will simply leave the unwanted HP cores disconnected and therefore inactive. As a result, the metal interconnect space relating the inactive HP cores will be unused. This unused space results in a variation to the pattern density across the chip and therefore across the wafer. Unused space on the chip can also occur on chips that do not use HP cores or do not have any unused cores simply through the methods used to layout the connecting metal lines. An example of a portion of a metal layer 40 is shown in FIG. 2. The metal layer includes active structures 42 associated with active IP cores within active areas of the design or used as interconnect for customized logic. In addition, the metal layer includes large open areas 44 which relate to the inactive IP cores, other unused areas of the floor plan, or simply as a result of the interconnect layout routing. Thus, the metal layer layout includes a variation in pattern density across the chip.
As a result of the variation in pattern density, it is difficult for the CMP (chemical mechanical polishing) process to planarize properly. Attempts have been made to improve CMP processing and/or equipment to be less effected by changes in pattern density, however, only limited success has been achieved. Another way in which the CMP planarzation problem has been address is by using different planarization processes for chips of different pattern densities. Although limited success has been experienced with this method, special handling is often required to divide wafers of different devices and special software systems are required to provide different recipes for the different device types. Another method which has been used to alleviate the problems with variations in pattern densities is to place metal utilization dummy structures in the unused portions of the chip. i.e. the portions of the chip relating to the inactive IP cores. An example of this method is shown in FIG. 3. The metal layer 50 includes active structures 52 associated with the active IP cores and other active circuitry and dummy metal structures 54 which have been provided in the otherwise large open areas of the metal layer.
In addition to the limited success experienced with each of the methods currently used to address the problems with variations in pattern densities, these solutions do not address the un-utilized space on the chip. The creation of the silicon area relating to the inactive IP cores is costly to process, provides no value to the processed device, and as such can be seen as wasted.
Another problem currently encountered with chip manufacturing is the ability to detect defects. In particular, defects which occur as a result of Cu dual damascene processing are especially difficult to detect. The dual damascene process is often used to create inlaid metal patterns on the wafer. Two patterning steps are used to create features of two different depths which relate to the wiring level and the inter level connections. The patterns are then filled with metal and a polishing step is used to create the inlaid structure. Defects in chips made using the damascene process, are difficult to detect because the defects are buried in the bottom of trenches or occur at one of the many interface layers such as that between a via and a large metal line. Thus, the defects are not readily detected using common optical and laser reflectance based inspection tools.
One approach to finding hidden defects involves performing a failure analysis of the failing parts after the wafer test. The failure analysis after wafer test requires extensive work in order to isolate the fault to a particular area on the chip. In this case, the device must be de-processed to determine the cause of the defect. This approach can take a long time and can require an array of expensive equipment. As a result the success rate of finding the defect is only about 60%. In addition, after the problem is discovered, results from failure analysis can take as long as weeks or months to obtain.
Another approach to finding hidden defects involves the use of test chips with structures which can be electrically probed. These test chips are run in the same manufacturing line as the product chip, however, they are produced in a different lot, which of course is rim for the purpose of identifying defects and is not sold to the customer. Test chips with structures which can be electrically probed can be very effective in identifying issues in the manufacturing line, however, running lots for the purpose of creating test chips can be very expensive. In addition, the test chips only provide information about the test lot and therefore may not provide information needed about a particular lot. Therefore, it is difficult to use the test chips for quality checks or to trouble shoot specific problems. Another problem with using test structures for electrically probing is that the test structures can only be used at certain steps in the line. Finally, because Cu is a soft metal, probing can be difficult as it often results in damaging the Cu or spreading the defect.
A method to address the issue of detecting hidden defects that has been gaining recent attention is Voltage Contrast inspection. FIGS. 4a and 4b represent voltage contrast inspection structures. FIG. 4a represents a voltage contrast inspection structure in which no short is present and FIG. 4b represents a voltage contrast inspection structure which includes a short. As shown, voltage contrast inspection functions by placing electrically grounded structures 60a-60c next to electrically floating structures 62a-62c, typically these structures are in the form of lines. The structures to be kept at the same electrical potential are connected to each other through the inter metal layer vias or routed metal lines. An area to be scanned or inspection zone 64 is selected and a scanning electron microscope (SEM) is used to electrically charge the inspection zone 64. The whole structure need not be inspected to determine a fault, rather only the inspection zone 64 must be inspected. Different materials will pick up a different level of charge based upon its characteristics. Similar materials, such as metal, will charge up or not depending on if they are grounded or not. Using the SEM, the electron beam image will interact with the charge on the structures to be viewed. As a result the metal lines 60a-60c, 62a-62c will appear lighter or darker depending on if it is insulated (retaining charge) or grounded (not charged). Voltage contrast inspection takes advantage of this effect to detect the difference between floating structures 62a-62c and grounded structures 60a-60c. By placing a floating structure 62 next to a grounded structure 60 a very small electrical short can be detected by the change in contrast. An example of such a short 66 is shown in FIG. 4b. As a result of the short 66, the floating metal structure 62b appears dark rather than light. Thus, inspection of the inspection zone 64 reveals three adjacent dark structures 60b, 62b, 60c rather than alternating dark and light structures. As such the inspector or automated SEM based inspection tool is alerted to the defect. This technique is very sensitive and can detect currents shorting as low as 1 nano amp at a 1 volt potential.
One problem with voltage contrast inspection on the actual product wafers is that it is very slow since the entire chip area must be inspected. It is also ineffective since the layout of the chip will have many combinations and degrees of grounding and floating structures so that it is difficult to know just how much of the chip is actually inspected.
The present invention provides a chip which overcomes the problems in the prior art and which provides additional advantages over the prior art, such advantages will become clear upon reading of the attached specification in combination with a study of the drawings.